Engineering radiation-tolerant CMOS logic to prevent Single-Event Upsets (SEU) and latch-up in aerospace and tactical cryptographic hardware.
High-altitude aircraft and tactical satellites are bombarded by galactic cosmic rays, solar protons, and atmospheric neutrons. When heavy ions strike silicon nodes, they induce transient charge pulses causing Single-Event Upsets (bit flips) or destructive Single-Event Latch-up (SEL).
MilitaryTPM implements Triple Modular Redundancy (TMR) across all critical arithmetic logic units. Three parallel NTT multipliers execute every polynomial computation simultaneously; a majority voter circuit compares results on every clock cycle, correcting single-bit faults in real time.
By fabricating the crypto-core on a specialized Silicon-On-Insulator (SOI) process with deep oxide trenches, parasitic thyristor structures are eliminated, guaranteeing immunity to radiation-induced latch-up up to a Total Ionizing Dose (TID) exceeding 300 krad(Si).